This invention relates to the formation of Damascene copper interconnects for integrated circuits. More specifically, the invention provides an electroless procedure and conditions for filling features on the surfaces of integrated circuits.
The Damascene or dual Damascene process provides inlaid copper lines in dielectric layers of integrated circuits. The copper lines provide electrical routing between circuit elements in the integrated circuit. In a Damascene process, both copper lines and vias are provided in horizontal layers of dielectric.
The existing process flow used to form the copper lines and blind vias which comprise Damascene or dual Damascene interconnections between integrated circuit devices is typically as follows:
1. Form trench pattern in a dielectric layer on the wafer face using an etch resistant photoresist.
2. Etch features (trenches).
3. Remove resist.
4. Form via pattern in the dielectric layer on the wafer face using an etch resistant photoresist.
5. Etch Vias
6. Remove resist.
7. Deposit a diffusion barrier layer (e.g., tantalum by PVD) and a conductive seed layer (e.g., a copper seed by PVD).
8. Electroplate copper to fill etched features.
9. Polish copper off the wafer face leaving copper filled interconnect circuitry.
As indicated, the Damascene process typically employs physical vapor deposition (PVD) of first a diffusion barrier layer and then a copper seed layer. These layers are deposited in succession into vias and routing lines, pre-etched in dielectric surfaces. Many suitable barrier layers may be employed such as tantalum, titanium nitride, etc. The copper seed layer serves as a conductive substrate unto which bulk copper may be electrodeposited. The seed layer is a thin layer (typically 800-2000 angstroms nominal) that covers the entire face of the wafer, following the sharp contours of the recessed features.
With the barrier and seed layers in place, the electroplating operation can begin. Electroplating fills the etched vias and trenches with copper and continues until the copper forms a continuous sheet over the entire wafer surface. Thereafter, the top portion of the copper is removed from the wafer face to expose the unetched regions of the dielectric layer and leave copper-filled interconnect circuitry.
One limitation of this process sequence is the difficulty in achieving a continuous PVD copper seed layer within high aspect ratio features without causing the features to close off at the top. Understand that as greater and greater quantities of copper seed are deposited by PVD, more complete coverage within a deep feature is attained. But this comes at the expense of pinch-off at the top of the feature, as depicted in FIG. 1. As shown, pinch-off prematurely closes the upper portion (neck) of the trench or via, thereby preventing complete fill of the bottom portions of the feature. Note the void in the top center of the feature, which results from pinch-off.
The PVD process inherently deposits copper on the top or higher regions of a trench or via, thereby creating a narrow neck. This excess of copper at this neck of a recessed feature causes further build up during the subsequent electrodeposition process. Ultimately, the pinch-off region in the initial seed layer blocks further deposition in the lower regions of the feature and leaves a center void within the copper fill of the feature. It is now understood that pinch-off commonly occurs and when it does, it renders void-free filling by electrodeposition nearly impossible. This problem is particularly acute in high aspect ratio features of small width.
Reducing the amount of copper to a level which does not cause pinch-off leads to seed continuity problems near the base of high aspect ratio features as shown in FIG. 2. When the seed is discontinuous near the feature base the copper growth during the electrodeposition process is slow or negligible in these areas. As a result, a large void appears at the base of poorly seeded feature following electrodeposition because the electrodeposition process takes place only above the feature base on areas of thicker seed. The resulting fill profile, showing a void at the feature base following electrodeposition, is also shown in FIG. 2.
Various options intended to provide seed layers suitable for extended Damascene fill by electrodeposition have been described. These include PVD/CVD Cu bilayers, all CVD seed, barrier optimization to improve PVD Cu smoothness at low thickness, atomic layer deposition, wet process seed deposition (Y. Lantasov, R. Palmans, K. Maex, Advanced Metallization Conf. Proc, pp 30-31, Oct. 3-5, 2000), and augmentation of PVD seed using wet processes (L. Chen, T. Ritzdorf, Semicon. Fabtech, July 2000). None of these is entirely suitable.
It is now understood that significant hurdles in copper fill technology must be overcome for future generation Damascene processes.